View M58WR064FB60ZB6_664367.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58WR064FT M58WR064FB
64 Mbit (4Mb x16, Multiple Bank, Burst) 1.8V Supply Flash Memory
FEATURES SUMMARY

SUPPLY VOLTAGE - VDD = 1.7V to 2V for Program, Erase and Read - VDDQ = 1.7V to 2.24V for I/O Buffers - VPP = 12V for fast Program (optional) SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode: 66MHz - Asynchronous/ Synchronous Page Read mode - Random Access: 60ns, 70ns, 80ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME - 8s by Word typical for Fast Factory Program - Double/Quadruple Word Program option - Enhanced Factory Program options MEMORY BLOCKS - Multiple Bank Memory Array: 4 Mbit Banks - Parameter Blocks (Top or Bottom location) DUAL OPERATIONS - Program Erase in one Bank while Read in others - No delay between Read and Write operations BLOCK LOCKING - All blocks locked at Power up - Any combination of blocks can be locked - WP for Block Lock-Down SECURITY - 128 bit user programmable OTP cells - 64 bit unique device number COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK
Figure 1. Package
FBGA
VFBGA56 (ZB) 7.7 x 9 mm
ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Codes: M58WR064FT (Top): 8810h M58WR064FB (Bottom): 8811h PACKAGE - Compliant with Lead-Free Soldering Processes - Lead-Free Versions
October 2004
1/87
M58WR064FT, M58WR064FB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Table 1. Figure 3. Table 2. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Factory Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 9. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Synchronous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 11. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 14. Program/Erase Times and Endurance Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 16.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 19.VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline . . . 53 Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data . . . . . . 53 Figure 20.VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 54 Figure 21.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . . 55 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 28. Top Boot Block Addresses, M58WR064FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 29. Bottom Boot Block Addresses, M58WR064FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 31. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 35. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 36. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 37. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 38. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 39. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 23.Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 24.Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 25.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 73 Figure 26.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 27.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 75
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Figure 28.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 29.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 77 Figure 30.Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 31.Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Quadruple Enhanced Factory Program Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 40. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 41. Command Interface States - Modify Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 42. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 43. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 85 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 44. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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SUMMARY DESCRIPTION
The M58WR064FT/B is a 64 Mbit (4Mbit x16) nonvolatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7V to 2V VDD supply for the circuitry and a 1.7V to 2.24V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. The VPP pin can also be used as a control pin to provide absolute protection against program or erase. The device features an asymmetrical block architecture. M58WR064FT/B has an array of 135 blocks, and is divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2., and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58WR064FT, and at the bottom for the M58WR064FB. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst mode, data is output on each clock cycle at frequencies of up to 66MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The M58WR064FT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at PowerUp. The device includes a Protection Register to increase the protection of a system's design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment OneTime-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 5. shows the Protection Register Memory Map. The memory is offered in a VFBGA56, 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch package. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to '1').
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Figure 2. Logic Diagram Table 1. Signal Names
A0-A21 Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Wait Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally
VDD VDDQ VPP 22 A0-A21 W E G RP WP L K M58WR064FT M58WR064FB WAIT 16 DQ0-DQ15
DQ0-DQ15 E G W RP WP K L WAIT VDD VDDQ
VSS
VSSQ
AI07747c
VPP VSS VSSQ NC
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M58WR064FT, M58WR064FB
Figure 3. VFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
A11
A8
VSS
VDD
VPP
A18
A6
A4
B
A12
A9
A20
K
RP
A17
A5
A3
C
A13
A10
A21
L
W
A19
A7
A2
D
A15
A14
WAIT
A16
DQ12
WP
NC
A1
E
VDDQ
DQ15
DQ6
DQ4
DQ2
DQ1
E
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
G
G
DQ7
VSSQ
DQ5
VDD
DQ3
VDDQ
DQ8
VSSQ
AI06189
Table 2. Bank Architecture
Number Parameter Bank Bank 1 Bank 2 Bank 3 ---Bank Size 4 Mbits 4 Mbits 4 Mbits 4 Mbits ---Parameter Blocks 8 blocks of 4 KWords ---Main Blocks 7 blocks of 32 KWords 8 blocks of 32 KWords 8 blocks of 32 KWords 8 blocks of 32 KWords ---8 blocks of 32 KWords 8 blocks of 32 KWords
Bank 14 Bank 15
4 Mbits 4 Mbits
-
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M58WR064FT, M58WR064FB
Figure 4. Memory Map
M58WR064FT - Top Boot Block Address lines A21-A0 000000h 007FFFh Bank 15 038000h 03FFFFh 32 KWord 32 KWord 8 Main Blocks Parameter Bank
M58WR064FB - Bottom Boot Block Address lines A21-A0 000000h 000FFFh 007000h 007FFFh 008000h 00FFFFh 038000h 03FFFFh 040000h 047FFFh Bank 1 078000h 07FFFFh 080000h 087FFFh Bank 2 0B8000h 0BFFFFh 0C0000h 0C7FFFh Bank 3 0F8000h 0FFFFFh 32 KWord 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 4 KWord 8 Parameter Blocks 4KWord 32 KWord 7 Main Blocks 32 KWord 32 KWord 8 Main Blocks
300000h 307FFFh Bank 3 338000h 33FFFFh 340000h 347FFFh Bank 2 378000h 37FFFFh 380000h 387FFFh Bank 1 3B8000h 3BFFFFh 3C0000h 3C7FFFh 3F0000h 3F7FFFh 3F8000h 3F8FFFh 3FF000h 3FFFFFh
32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 7 Main Blocks 32 KWord 4 KWord 8 Parameter Blocks 4 KWord Bank 15
Parameter Bank
3C0000h 3C7FFFh 3F8000h 3FFFFFh
32 KWord 8 Main Blocks 32 KWord
AI07748c
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M58WR064FT, M58WR064FB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Output Enable (G). The Output Enable input controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable input controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 13., Lock Status). Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 18., DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 19., DC Characteristics - Voltages). Latch Enable (L). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at V IH . Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K). The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous read and in write operations. Wait (WAIT). Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is not gated by Output Enable. VDD Supply Voltage . VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is a power supply pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. The pin can also be used as a control input. In the device the two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Tables 18 and 19, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS
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Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 9., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
BUS OPERATIONS
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 10, 11, 12 and 13 Read AC Waveforms, and Tables 20 and 21 Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case Table 3. Bus Operations
Operation Bus Read Bus Write Address Latch Output Disable Standby Reset
Note: 1. 2. 3. 4.
the Latch Enable should be tied to VIH during the bus write operation. See Figures 16 and 17, Write AC Waveforms, and Tables 22 and 23, Write AC Characteristics, for details of the timing requirements. Address Latch. Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable. Output Disable. The outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable and Reset are at VIH. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Reset. During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
E VIL VIL VIL VIL VIH X
G VIL VIH X VIH X X
W VIH VIL VIH VIH X X
L VIL(2) VIL(2) VIL X X X
RP VIH VIH VIH VIH VIH VIL
WAIT(4)
DQ15-DQ0 Data Output Data Input Data Output or Hi-Z (3) Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
X = Don't care. L can be tied to VIH if the valid address has been previously latched. Depends on G. WAIT signal polarity is configured using the Set Configuration Register command.
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COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Refer to Table 4., Command Codes, and APPENDIX D., Tables 40, 41, 42 and 43, Command Interface States - Modify and Lock Tables, for a summary of the Command Interface. The Command Interface is split into two types of commands: Standard commands and Factory Program commands. The following sections explain in detail how to perform each command. Table 4. Command Codes
Hex Code 01h 03h 10h 20h 2Fh 30h 35h 40h 50h 56h 60h 70h 75h 80h 90h 98h B0h C0h Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Enhanced Factory Program Setup Double Word Program Setup Program Setup Clear Status Register Quadruple Word Program Setup Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Quadruple Enhanced Factory Program Setup Bank Erase Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block Unlock Confirm or Enhanced Factory Program Confirm Read Array
D0h
FFh
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COMMAND INTERFACE - STANDARD COMMANDS
The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5., Standard Commands, in conjunction with the following text descriptions. Read Array Command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and return the addressed bank to Read Array mode. Subsequent read operations will read the addressed location and output the data. A Read Array command can be issued in one bank while programming or erasing in another bank. However if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be executed but the output data is not guaranteed. Read Status Register Command The Status Register indicates when a Program or Erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. See Table 8. for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within one of the banks. A subsequent Read operation in the same bank will output the Manufacturer Code, the Device Code, the protection Status of the blocks in the targeted bank, the Protection Register, or the Configuration Register (see Table 6.). If a Read Electronic Signature command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Electronic Signature mode, subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read CFI Query mode, subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to Program or Erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. The status of the other banks is not affected by the command (see Table 11.). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to Read Array mode. See APPENDIX B., COMMON FLASH INTERFACE, Tables 30, 31, 32, 33, 34, 35, 36, 37, 38 and 39 for details on the information contained in the Common Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to `0') error bits SR1, SR3, SR4 and SR5 in the Status Register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not change the Read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, regardless of whether the block has been programmed or not. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. The second latches the block address in the Program/Erase Controller and starts it.
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If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14., Program/Erase Times and Endurance Cycles. See APPENDIX C., Figure 26., Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The memory array can be programmed word-byword. Only one Word in one bank can be programmed at any one time. Two bus write cycles are required to issue the Program Command. The first bus cycle sets up the Program command. The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 14., Program/ Erase Times and Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See APPENDIX C., Figure 22., Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The command can be addressed to any bank. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the erase-suspended block or the program-suspended Word), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block LockDown or Block Unlock commands will also be accepted. The block being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See APPENDIX C., Figure 25., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 27., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the
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programming operation then read the array. See APPENDIX C., Figure 25., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 27., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. The first bus cycle sets up the Protection Register Program command. The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 5., Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. See APPENDIX C., Figure 29., Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command The Set Configuration Register command is used to write a new value to the Configuration Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. The first cycle writes the setup command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command. Read operations output the memory array content after the Set Configuration Register command is issued. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13. shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See APPENDIX C., Figure 28., Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13. shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and APPENDIX C., Figure 28., Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A lockeddown block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address.
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The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 13. shows the Lock Status afTable 5. Standard Commands
Cycles Bus Operations 1st Cycle Op.
Write Write Write Write Write Write Write Write Write Write Write Write Write Write
ter issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and APPENDIX C., Figure 28., Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command.
Commands
2nd Cycle Data
FFh 70h 90h 98h 50h 20h 40h or 10h B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write Write Write BA WA D0h PD
Add
BKA BKA BKA BKA BKA BKA or BA(3)
Op.
Read Read Read Read
Add
WA BKA(2) BKA(2) BKA(2)
Data
RD SRD ESD QD
Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down
1+ 1+ 1+ 1+ 1 2 2 1 1 2 2 2 2 2
BKA or WA(3) X X PRA CRD BKA or BA(3) BKA or BA(3) BKA or BA(3)
PRA CRD BA BA BA
PRD 03h 01h D0h 2Fh
Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6. 3. Any address within the bank can be used.
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Table 6. Electronic Signature Codes
Code Manufacturer Code Top (M58WR064FT) Device Code Bottom(M58WR064FB) Locked Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Reserved Configuration Register ST Factory Default Protection Register Lock OTP Area Permanently Locked Bank Address + 81 Bank Address + 84 Protection Register Bank Address + 85 Bank Address + 8C
Note: CR=Configuration Register.
Address (h) Bank Address + 00 Bank Address + 01 Bank Address + 01
Data (h) 0020 8810 8811 0001 0000
Block Address + 02 0003 0002 Bank Address + 03 Bank Address + 05 Bank Address + 80 0000 Unique Device Number OTP Area Reserved CR 0002
Figure 5. Protection Register Memory Map
PROTECTION REGISTER 8Ch User Programmable OTP 85h 84h Unique device number 81h 80h Protection Register Lock 1 0
AI08149
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COMMAND INTERFACE - FACTORY PROGRAM COMMANDS
The Factory Program commands are used to speed up programming. They require VPP to be at VPPH except for the Bank Erase command which also operates at VPP = VDD. Refer to Table 7., Factory Program Commands, in conjunction with the following text descriptions. The use of Factory Program commands requires certain operating conditions. VPP must be set to VPPH (except for Bank Erase comand), VDD must be within operating range, Ambient temperature, TA must be 25C 5C, The targeted block must be unlocked. Bank Erase Command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to '1'. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Bank Erase operations can be performed at both VPP = VPPH and VPP = VDD. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Bank Erase command. The second latches the bank address in the Program/Erase Controller and starts it. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. For optimum performance, Bank Erase commands should be limited to a maximum of 100 Program/Erase cycles per Block. After 100 Program/ Erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. Dual Operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in Table 14., Program/Erase Times and Endurance Cycles. Double Word Program Command The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the programming has started. During Double Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations and the command cannot be suspended. Typical Program times are given in Table 14., Program/Erase Times and Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See APPENDIX C., Figure 23., Double Word Program Flowchart and Pseudo code, for the flowchart for using the Double Word Program command. Quadruple Word Program Command The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. Five bus write cycles are necessary to issue the Quadruple Word Program command. The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written.
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The third bus cycle latches the Address and the Data of the second word to be written. The fourth bus cycle latches the Address and the Data of the third word to be written. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Quadruple Word Program operations and the command cannot be suspended. Typical Program times are given in Table 14., Program/Erase Times and Endurance Cycles. See APPENDIX C., Figure 24., Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command. Enhanced Factory Program Command The Enhanced Factory Program command can be used to program large streams of data within any one block. It greatly reduces the total programming time when a large number of Words are written to a block at any one time. Dual operations are not supported during the Enhanced Factory Program operation and the command cannot be suspended. For optimum performance the Enhanced Factory Program commands should be limited to a maximum of 10 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical Program times are given in Table 14. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 7., Factory Program Commands, and Figure 30., Enhanced Factory Program Flowchart. Setup Phase. The Enhanced Factory Program command requires two Bus Write operations to initiate the command.
The first bus cycle sets up the Enhanced Factory Program command. The second bus cycle confirms the command. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program. Program Phase. The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 7., Factory Program Commands, and Figure 30., Enhanced Factory Program Flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the Verify Phase. Verify Phase. The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and reprograms the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word. 2. Each subsequent Word to be verified is latched with a new Bus Write operation. The
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Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given with data FFFFh, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register. Exit Phase. Status Register P/E.C. bit SR7 set to `1' indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. Quadruple Enhanced Factory Program Command The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. Dual operations are not supported during Quadruple Enhanced Factory Program operations and the command cannot be suspended. The Quadruple Enhanced Factory Program command has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block. Setup Phase. The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program. Load Phase. The Load Phase requires 4 cycles to load the data (refer to Table 7., Factory Program Commands and Figure 31., Quadruple Enhanced Factory Program Flowchart). Once the first Word of each Page is written it is impossible to exit the Load phase until all four Words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address with data FFFFh is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit SR7 set to `0'). This check is not required for subsequent Load Phases. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. The memory is now set to enter the Program and Verify Phase. Program and Verify Phase. In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to `0', and that the device is not waiting for new data, Status Register bit SR0 set to `1'. When Status Register bit SR0 is set to `0' the Program and Verify phase has terminated. Once the Verify Phase has successfully completed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new Words to be programmed. Exit Phase. Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases. Status Register bit SR7 set to `1' and bit SR0 set to `0' indicate that the Quadruple Enhanced Factory Program command has terminated. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If
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the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register. Table 7. Factory Program Commands
Cycles Bus Write Operations 1st Add
BKA
Command
Phase
2nd Data
80h
3rd Data
D0h
Final -1 Data Add Data
Final Add Data
Add
BKA
Add
Bank Erase Double Word Program(4) Quadruple Word Program(5)
2
3
BKA or WA1(8) BKA or WA1(8) BKA or WA1(8) WA1(2) BKA or WA1(8)
35h 56h 30h PD1 75h
WA1 WA1 BA or WA1(9) WA2(3) WA1(2)
PD1 PD1 D0h PD2 PD1
WA2 WA2 WA1(2) WA3(3) WA2(7)
PD2 PD2 PD1 PD3 PD2 WA3 PD3 WA4 PD4
5
Enhanced Setup, Program Factory (6) Program Verify, Exit Setup, first Load First Program & Quadruple Verify Enhanced Subsequent Factory Program Loads
(5,6)
2+ n+1 n+1
5
WAn(3) PAn WAn(3) PAn
NOT FFFFh WA1(2) NOT FFFFh WA1(2) PD4
WA3(7) PD3 WA4(7)
Automatic WA1i
(2)
4
PD1i
WA2i
(7)
PD2i
WA3i
(7)
PD3i
WA4i
(7)
PD4i
Subsequent Program & Verify Exit 1 NOT WA1
(2)
Automatic
FFFFh
Note: 1. 2. 3. 4. 5. 6.
WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1. Address can remain Starting Address WA1 or be incremented. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed. 7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent Words in each Page can be written to any address. 8. Any address within the bank can be used. 9. Any address within the block can be used.
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STATUS REGISTER
The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 8., Status Register Bits. Refer to Table 8. in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status Bit (SR6). The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4). The Program Status bit is used to identify a Program failure or an attempt to program a `1' to an already programmed bit when VPP = VPPH. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. After an attempt to program a '1' to an already programmed bit, the Program Status bit SR4 only goes High (set to '1') if VPP = VPPH (if VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown). The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status Bit (SR3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program
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or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Bank Write/Multiple Word Program Status Bit (SR0). The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next Word. Note: Refer to APPENDIX C., FLOWCHARTS AND PSEUDO CODES, for using the Status Register.
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Table 8. Status Register Bits
Bit SR7 Name P/E.C. Status Type Status '0' '1' SR6 Erase Suspend Status Status '0' '1' SR5 Erase Status Error '0' '1' SR4 Program Status Error '0' '1' SR3 VPP Status Error '0' '1' SR2 Program Suspend Status Status '0' '1' SR1 Block Protection Status Error '0' No operation to protected blocks SR7 = `1' Not Allowed '1' SR7 = `0' Bank Write Status Status '0' SR0 Multiple Word Program Status (Enhanced Factory Program mode) '1' SR7 = `0' the device is NOT ready for the next word Status SR7 = `1' the device is exiting from EFP '0' SR7 = `0'
Note: Logic level '1' is High, '0' is Low.
Logic Level '1' Ready Busy Erase Suspended
Definition
Erase In progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort
Program or erase operation in a bank other than the addressed bank
SR7 = `1' No Program or erase operation in the device SR7 = `0' Program or erase operation in addressed bank SR7 = `1' Not Allowed
the device is ready for the next Word
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CONFIGURATION REGISTER
The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 9. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to'1' for asynchronous access. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 9., Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) tK tACC - tAVK_CPU + tQVK_CPU (n + 2) tK tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code tK is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last tDELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tACC is the random access time of the device. Refer to Figure 6., X-Latency and Data Output Configuration Example. Wait Polarity Bit (CR10) In synchronous burst mode the Wait signal indicates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait signal. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High. Data Output Configuration Bit (CR9) The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration Bit is '1' the output data is valid for two clock cycles. The Data Output Configuration depends on the condition: tK > tKQV + tQVK_CPU where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 6., X-Latency and Data Output Configuration Example. Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait bit is '0' the Wait output pin is asserted during the wait state. When the Wait bit is '1' the Wait output pin is asserted one clock cycle before the wait state. Burst Type Bit (CR7) The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' the memory outputs from sequential addresses. See Table 10., Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary
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(no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8, 16 Words nowrap, depending on the starting address, the deTable 9. Configuration Register
Bit CR15 CR14 010 011 100 CR13-CR11 X-Latency 101 111 Description 0 Read Select 1 Asynchronous Read (Default at power-on) Reserved 2 clock latency 3 clock latency 4 clock latency 5 clock latency Reserved (default) Value Synchronous Read Description
vice asserts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 Word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 Word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10., Burst Type Definition. CR14, CR5 and CR4 are reserved for future use.
Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration Wait Configuration 0 1 0 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 0 CR3 Wrap Burst 1 001 010 CR2-CR0 Burst Length 011 111 Valid Clock Edge 1 Sequential (default) Falling Clock edge Rising Clock edge (default) Reserved Wrap No Wrap (default) 4 Words 8 Words 16 Words Continuous (CR7 must be set to `1') (default) WAIT is active High (default) Data held for one clock cycle Data held for two clock cycles (default) WAIT is active during wait state WAIT is active one data cycle before wait state (default) Interleaved WAIT is active Low
CR8
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Table 10. Burst Type Definition
4 Words Start Add Sequen-tial Interleaved 0 0-1-2-3 Mode 8 Words Sequential Interleaved 16 Words Sequential Interleaved Continuous Burst
0-1-2-3 0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-70-1-2-3-4-5- 0-1-2-3-4-5-6-7-8-98-9-10-11-126-7 10-11-12-13-14-15 13-14-15
0-1-2-3-4-5-6...
1
1-2-3-0
1-0-3-2 1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9- 1-0-3-2-5-4-7-6- 1-2-3-4-5-6-71-0-3-2-5-410-11-12-13-14-15- 9-8-11-10-13- ...15-WAIT-16-177-6 0 12-15-14 18... 2-3-0-1-6-7- 2-3-4-5-6-7-8-9-104-5 11-12-13-14-15-0-1 2-3-0-1-6-7-4-5- 2-3-4-5-6-7...1510-11-8-9-14- WAIT-WAIT-1615-12-13 17-18...
2
2-3-0-1
2-3-0-1 2-3-4-5-6-7-0-1
3 ...
3-0-1-2
3-2-1-0 3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4- 3-4-5-6-7...153-2-1-0-7-6- 3-4-5-6-7-8-9-10-1111-10-9-8-15WAIT-WAIT5-4 12-13-14-15-0-1-2 14-13-12 WAIT-16-17-18...
Wrap
7
7-4-5-6
7-6-5-4 7-0-1-2-3-4-5-6
7-8-9-10-11-127-6-5-4-3-2-1-07-6-5-4-3-2- 7-8-9-10-11-12-1313-14-15-WAIT15-14-13-12-111-0 14-15-0-1-2-3-4-5-6 WAIT-WAIT-1610-9-8 17...
... 12 13 14 15 12-13-14-15-1617-18... 13-14-15-WAIT16-17-18... 14-15-WAITWAIT-16-17-18.... 15-WAIT-WAITWAIT-16-17-18...
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4 Words Start Add Sequen-tial Interleaved 0 0-1-2-3 8 Words Sequential 0-1-2-3-4-5-6-7 Interleaved 16 Words Sequential 0-1-2-3-4-5-6-7-8-910-11-12-13-14-15 1-2-3-4-5-6-7-8-910-11-12-13-14-15WAIT-16 2-3-4-5-6-7-8-9-1011-12-13-14-15WAIT-WAIT-16-17 3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-WAIT16-17-18 Interleaved Continuous Burst
Mode
1
1-2-3-4
1-2-3-4-5-6-7-8
2
2-3-4-5
2-3-4-5-6-7-89...
3
3-4-5-6
3-4-5-6-7-8-910
... No-wrap 7-8-9-10-11-1213-14 7-8-9-10-11-12-1314-15-WAIT-WAITWAIT-16-17-18-1920-21-22 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst)
7
7-8-9-10
... 12 12-13-14-15 12-13-14-1516-17-18-19 13-14-15WAIT-16-1718-19-20 14-15-WAITWAIT-16-1718-19-20-21 15-WAIT-WAITWAIT-16-1718-19-20-21-22 12-13-14-15-16-1718-19-20-21-22-2324-25-26-27 13-14-15-WAIT-1617-18-19-20-21-2223-24-25-26-27-28 14-15-WAIT-WAIT16-17-18-19-20-2122-23-24-25-26-2728-29 15-WAIT-WAITWAIT-16-17-18-1920-21-22-23-24-2526-27-28-29-30
13
13-14-15WAIT-16 14-15WAITWAIT-16-17 15-WAITWAITWAIT-1617-18
14
15
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Figure 6. X-Latency and Data Output Configuration Example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
E
L
A21-A0 tDELAY
VALID ADDRESS tAVK_CPU tACC tQVK_CPU tKQV tK tQVK_CPU
DQ15-DQ0 VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
AI06182
Figure 7. Wait Configuration Example
E
K
L
A21-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI06972
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READ MODES
Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in another (see Tables 11 and 12). Asynchronous Read Mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for Asynchronous operations. In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode. The first read operation within the Page has a longer access time (Tacc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always asserted. See Table 20., Asynchronous Read AC Characteristics, Figure 10., Asynchronous Random Access Read AC Waveforms, and Figure 11., Asynchronous Page Read AC Waveforms, for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4, 8, 16 Words, or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 16 Word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X latency, the Wait state and at the end of 4-, 8- or 16-Word burst. It is only deasserted when output data are valid. In Continuous Burst Read mode a Wait state will occur when crossing the first 16 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. The WAIT signal is meaningful only in Synchronous Burst Read mode, in other
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modes, WAIT is always asserted (except for Read Array mode). See Table 21., Synchronous Read AC Characteristics, and Figure 12., Synchronous Burst Read AC Waveforms, for details. Synchronous Burst Read Suspend. A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) in which case the initial latency time can be reduced to zero, or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when E is low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal is then halted at VIH or at VIL, and G goes high. When G becomes low again and the clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E remains active and will not revert to high-impedance when G goes high. So if two or more devices are connected to the system's READY signal, to prevent bus contention the WAIT signal of the Flash memory should not be directly connected to the system's READY signal. See Table 21., Synchronous Read AC Characteristics and Figure 14., Synchronous Burst Read Suspend AC Waveforms, for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always asserted. See Table 21., Synchronous Read AC Characteristics and Figure 13., Single Synchronous Read AC Waveforms, for details.
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DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the M58WR064FT/B provides flexibility for software developers by allowing code and data to be split with 4Mbit granularity. The Dual Operations feature simplifies the software management of the device and allows code to be executed from one bank while another bank is being programmed or erased. The Dual operations feature means that while programming or erasing in one bank, Read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in Program or Erase mode). If a Read operation is required in a bank which is programming or erasing, the Program or Erase operation can be suspendTable 11. Dual Operations Allowed In Other Banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Status Register Yes Yes Yes Yes Yes Read CFI Query Yes Yes Yes Yes Yes Read Electronic Program Signature Yes Yes Yes Yes Yes Yes - - - Yes Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
ed. Also if the suspended operation was Erase then a Program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in Read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of program or erase operations. The combination of these features means that read operations are possible at any moment. Tables 11 and 12 show the dual operations possible in other banks and in the same bank. For a complete list of possible commands refer to APPENDIX D., COMMAND INTERFACE STATE TABLES.
Idle Programming Erasing Program Suspended Erase Suspended
Table 12. Dual Operations Allowed In Same Bank
Commands allowed in same bank Status of bank Read Array Yes -
(2)
Read Read Read Status Electronic Program CFI Query Register Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - - - Yes(1)
Block Erase Yes - - - -
Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
-(2) Yes(1) Yes(1)
Note: 1. Not allowed in the Block or Word that is being erased or programmed. 2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
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BLOCK LOCKING
The M58WR064FT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows softwareonly control of block locking.
Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13., defines all of the possible protection states (WP, DQ1, DQ0), and APPENDIX C., Figure 28., shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6., will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate
software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is Low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was High. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to APPENDIX D., COMMAND INTERFACE STATE TABLES, for detailed information on which commands are valid during erase suspend.
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Table 13. Lock Status
Current Protection Status(1) (WP, DQ1, DQ0) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 Program/Erase Allowed yes no yes no yes no no After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 Next Protection Status(1) (WP, DQ1, DQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 14. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block or bank are at `0' (preprogrammed). The worst case is when all the bits in the block or bank are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. In the M58WR064FT/B the maximum number of Program/ Erase cycles depends on the VPP voltage supply used.
Table 14. Program/Erase Times and Endurance Cycles
Parameter Parameter Block (4 KWord)(2) Preprogrammed Erase Main Block (32 KWord) Not Preprogrammed Preprogrammed Bank (4Mbit) Not Preprogrammed VPP = VDD Word Program Program
(3)
Condition
Min
Typ 0.3 0.8 1 4.5 6 10 32 256 5 5
Typical after 100k W/E Cycles 1 3
Max 2.5 4 4
Unit s s s s s
10
100
s ms ms
Parameter Block (4 KWord) Main Block (32 KWord)
Suspend Latency Program/ Erase Cycles (per Block)
Program Erase Main Blocks Parameter Blocks Parameter Block (4 KWord) 100,000 100,000
10 20
s s cycles cycles
0.25 0.8 6 8 8 32
(4)
2.5 4
s s s
Erase
Main Block (32 KWord) Bank (4Mbit) Word/ Double Word/ Quadruple Word (4) Parameter Block (4 KWord) Quadruple Word(4) Word Quadruple Word Word Quad-Enhanced Factory Program(4) Quadruple Word(4)
100
s ms ms ms ms s s
VPP = VPPH
Program(3)
64 256 0.7 0.5 1000 2500
Main Block (32 KWord)
Bank (4Mbit)
Program/ Erase Cycles (per Block)
Note: 1. 2. 3. 4.
Main Blocks Parameter Blocks
cycles cycles
TA = -40 to 85C; VDD = 1.7V to 2.2V; VDDQ = 2.2V to 3.3V. The difference between Preprogrammed and not preprogrammed is not significant (30ms). Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). Measurements performed at 25C. TA = 25C 5C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program.
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MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 15. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG TLEAD VIO VDD VDDQ VPP IO tVPPH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature During Soldering Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -0.5 -0.2 -0.2 -0.2 -40 -40 -65 Max 85 125 155
(1)
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C C C V V V V mA hours
VDDQ+0.6 2.45 2.45 14 100 100
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK (R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 16., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
M58WR064FT, M58WR064FB 60 Parameter Min VDD Supply Voltage VDDQ Supply Voltage VPP Supply Voltage (Factory environment) VPP Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 1.7 1.7 11.4 -0.4 - 40 30 5 0 to VDDQ VDDQ/2 Max 2 2.24 12.6 VDDQ +0.4 85 Min 1.7 1.7 11.4 -0.4 - 40 30 5 0 to VDDQ VDDQ/2 Max 2 2.24 12.6 VDDQ +0.4 85 Min 1.7 1.7 11.4 -0.4 - 40 30 5 0 to VDDQ VDDQ/2 Max 2 2.24 12.6 VDDQ +0.4 85 V V V V C pF ns V V 70 80 Units
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
VDDQ
VDDQ VDDQ/2 0V VDDQ VDD 16.7k
AI06161
DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI06162
Table 17. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF
Note: Sampled only, not 100% tested.
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M58WR064FT, M58WR064FB
Table 18. DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word Supply Current Synchronous Read (f=54MHz) IDD1 8 Word 16 Word Continuous 4 Word Supply Current Synchronous Read (f=66MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) RP = VSS 0.2V E = VDD 0.2V E = VIL, G = VIH VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank E = VDD 0.2V VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD 3 7 10 12 13 8 11 14 16 10 10 10 8 10 8 10 13 Min Typ Max 1 1 6 16 18 22 25 17 20 25 30 50 50 50 15 20 15 20 26 Unit A A mA mA mA mA mA mA mA mA mA A A A mA mA mA mA mA
Supply Current IDD6 (1,2) (Dual Operations)
23
45
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby) VPP Supply Current (Program)
10 2 0.2 2 0.2 0.2 0.2
50 5 5 5 5 5 5
A mA A mA A A A
IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) VPP Supply Current (Read) VPP Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents.
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M58WR064FT, M58WR064FB
Table 19. DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.1 11.4 1.8 12 3.3 12.6 0.4 Test Condition Min -0.5 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
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A0-A21 VALID VALID tAVAV
tAVLH
tLHAX
tAXQX
L tLLLH tLLQV tELLH tELQV tLHGL
E tELQX tEHQZ tEHQX
G tGLQV tGLQX tELTV tGHQX tGHQZ tEHTZ
Figure 10. Asynchronous Random Access Read AC Waveforms
Hi-Z
WAIT
tAVQV VALID
DQ0-DQ15
Hi-Z
Valid Address Latch
Outputs Enabled
Data Valid
Standby
M58WR064FT, M58WR064FB
Note. Write Enable, W, is High, WAIT is active Low.
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AI08150
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VALID ADDRESS tAVAV VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS tAVLH tLHAX tLLLH tLLQV tELLH tLHGL tELQV tELQX tELTV tGLQV tGLQX VALID DATA tAVQV1 VALID DATA VALID DATA VALID DATA Outputs Enabled Valid Data Standby
AI08151
A2-A21
M58WR064FT, M58WR064FB
A0-A1
L
Figure 11. Asynchronous Page Read AC Waveforms
E
G
WAIT (1)
Hi-Z
DQ0-DQ15
Valid Address Latch
Note 1. WAIT is active Low.
M58WR064FT, M58WR064FB
Table 20. Asynchronous Read AC Characteristics
Symbol tAVAV tAVQV tAVQV1 tAXQX (1) tELTV Read Timings tELQV (2) tELQX (1) tEHTZ tEHQX
(1)
Alt tRC tACC tPAGE tOH
Parameter Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable Low to Wait Valid Min Max Max Min Max Max Min Max Min Max Max Min Min Max Min Min Min Min Max Min
M58WR064FT/B 60 60 60 20 0 11 60 0 14 0 14 20 0 0 14 7 10 7 7 60 0 70 70 70 20 0 14 70 0 17 0 17 20 0 0 14 9 10 9 9 70 0 80 80 80 25 0 14 80 0 17 0 17 25 0 0 14 9 10 9 9 80 0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCE tLZ
Chip Enable Low to Output Valid Chip Enable Low to Output Transition Chip Enable High to Wait Hi-Z
tOH tHZ tOE tOLZ tOH tDF tAVADVH tELADVH tADVHAX tADVLADVH tADVLQV tADVHGL
Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Latch Enable Pulse Width Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low
tEHQZ (1) tGLQV (2) tGLQX (1) tGHQX (1) tGHQZ (1) tAVLH Latch Timings tELLH tLHAX tLLLH tLLQV tLHGL
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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VALID VALID tKHQX VALID VALID tKHQV NOT VALID tLLLH tEHQX tEHQZ Note 1 tEHEL tGHQX tGLQX tGHQZ tKHTV Note 2 tKHTX Note 2 Note 2 Valid Valid Data Flow Data tEHTZ X Latency Boundary Crossing Standby
AI08152b
DQ0-DQ15
Hi-Z
A0-A21
VALID ADDRESS
M58WR064FT, M58WR064FB
tAVLH
L
tLLKH
tAVKH
K(3)
Figure 12. Synchronous Burst Read AC Waveforms
tELKH
tKHAX
E
G
tELTV
Hi-Z
WAIT
Address Latch
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge. Here the active edge of K is the rising one.
DQ0-DQ15
VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID
Hi-Z
A0-A21
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX tEHEL
Figure 13. Single Synchronous Read AC Waveforms
E tGLQX tGLQV tGHQX tGHQZ
G tEHTZ tKHTV Note 3
Hi-Z
tELTV
WAIT(2)
M58WR064FT, M58WR064FB
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode. WAIT signals valid data if the addressed bank is in Read Array mode. 4. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge. Here the active edge of K is the rising one.
AI06973c
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VALID VALID NOT VALID NOT VALID
Hi-Z
DQ0-DQ15
A0-A21
VALID ADDRESS
tAVLH tLLLH
M58WR064FT, M58WR064FB
L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX
E tGLQX tGLQV tGHQZ tGHQX
Figure 14. Synchronous Burst Read Suspend AC Waveforms
G tEHTZ
tELTV
Hi-Z
WAIT(2)
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one.
AI08353b
M58WR064FT, M58WR064FB
Figure 15. Clock input AC Waveform
tKHKL
tKHKH
tf
tr
tKLKH
AI06981
Table 21. Synchronous Read AC Characteristics
M58WR064FT/B Symbol Alt Parameter 60 tAVKH tELKH Synchronous Read Timings tELTV tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH tKHKL tKLKH tf tr tCLKHAX tCLKHQV tAVCLKH tELCLKH Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Latch Enable Low to Clock High Clock Period (f=54MHz) tCLK Clock Period (f=66MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time Min Min 15 3.5 4.5 4.5 ns ns Min Min Max Min Max Min Max 7 7 11 14 11 7 11 70 9 9 14 14 14 9 14 80 9 9 14 14 14 9 14 ns ns ns ns ns ns ns Unit
tCLKHQX tADVLCLKH
Min Min Min
3 7
4 9 18.5
4 9 18.5
ns ns ns
Max
3
3
3
ns
Note: 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 20., Asynchronous Read AC Characteristics.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVWH tWHAV tWHAX VALID ADDRESS tLHAX tLLLH tWHLL tWHEH tWHWL tWHGL tWLWH tWHEL tWHDX COMMAND CMD or DATA tWHWPL tWPHWH tQVWPL tWHQV STATUS REGISTER tELQV tWHVPL tVPHWH tQVVPL tELKV CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI06974
A0-A21
tAVLH
L
tELLH
M58WR064FT, M58WR064FB
E
tELWL
G
tGHWL
W
tDVWH
Figure 16. Write AC Waveforms, Write Enable Controlled
DQ0-DQ15
WP
VPP
K
SET-UP COMMAND
M58WR064FT, M58WR064FB
Table 22. Write AC Characteristics, Write Enable Controlled
M58WR064FT/B Symbol tAVAV tAVLH tAVWH(3) tDVWH tELLH tELWL tELQV Write Enable Controlled Timings tELKV tGHWL tLHAX tLLLH tWHAV(3) tWHAX(3) tWHDX tWHEH tWHEL(2) tWHGL tWHLL tWHWL tWHQV tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH tVPS tWP tWPH tAH tDH tCH tCS tWC tDS Alt tWC Parameter 60 Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable Low to Clock Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low Write Enable High to Write Enable Low Write Enable High to Output Valid Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 60 7 40 40 10 0 60 7 14 7 7 0 0 0 0 20 0 0 20 80 40 0 0 200 200 200 200 70 70 9 45 45 10 0 70 9 17 9 9 0 0 0 0 25 0 0 25 95 45 0 0 200 200 200 200 80 80 9 50 50 10 0 80 9 17 9 9 0 0 0 0 25 0 0 25 105 50 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns. 3. Meaningful only if L is always kept low.
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PROGRAM OR ERASE tAVAV BANK ADDRESS tLHAX tAVEH tEHAX tLLLH VALID ADDRESS VALID ADDRESS tELLH tEHWH tEHEL tEHGL tELEH tWHEL tEHDX COMMAND CMD or DATA tEHWPL tWPHEH tQVWPL tWHQV STATUS REGISTER tELQV tEHVPL tVPHEH tQVVPL tELKV CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI06975
A0-A21
tAVLH
L
M58WR064FT, M58WR064FB
W
tWLEL
G
tGHEL
E
tDVEH
Figure 17. Write AC Waveforms, Chip Enable Controlled
DQ0-DQ15
WP
VPP
K
SET-UP COMMAND
M58WR064FT, M58WR064FB
Table 23. Write AC Characteristics, Chip Enable Controlled
M58WR064FT/B Symbol tAVAV tAVEH tAVLH tDVEH tEHAX tEHDX Chip Enable Controlled Timings tEHEL tEHGL tEHWH tELKV tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL(2) tWHQV tWLEL tEHVPL Protection Timings tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH tVPS tCS tCP tCH tDS tAH tDH tCPH Alt tWC tWC Parameter 60 Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Chip Enable Low to Clock Valid Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low Write Enable High to Output Valid Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low VPP High to Chip Enable High Write Protect High to Chip Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 60 40 7 40 0 0 20 0 0 7 40 10 60 14 7 7 20 80 0 200 200 0 0 200 200 70 70 45 9 45 0 0 25 0 0 9 45 10 70 17 9 9 25 95 0 200 200 0 0 200 200 80 80 50 9 50 0 0 25 0 0 9 50 10 80 17 9 9 25 105 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns.
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M58WR064FT, M58WR064FB
Figure 18. Reset and Power-up AC Waveforms
W, E, G, L
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI06976
tPLPH
Table 24. Reset and Power-up AC Characteristics
Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH (1,2) tVDHPH (3) Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition During Program During Erase Other Conditions Min Min Min 60 10 20 80 70 10 20 80 80 10 20 80 Unit s s ns
Min
30
30
30
ns
Min Min
50 50
50 50
50 50
ns s
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
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M58WR064FT, M58WR064FB
PACKAGE MECHANICAL
Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline
D FD FE SD D1
E
E1 BALL "A1" e e A A1 b A2 ddd
BGA-Z38
Note: Drawing is not to scale.
Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD 0.750 9.000 4.500 1.225 2.250 0.375 - 8.900 - - - - 0.660 0.350 7.700 5.250 0.300 7.600 - 0.400 7.800 - 0.080 - 9.100 - - - - 0.0295 0.3543 0.1772 0.0482 0.0886 0.0148 - 0.3504 - - - - 0.200 0.0260 0.0138 0.3031 0.2067 0.0118 0.2992 - 0.0157 0.3071 - 0.0031 - 0.3583 - - - - Min Max 1.000 0.0079 Typ Min Max 0.0394 inches
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M58WR064FT, M58WR064FB
Figure 20. VFBGA56 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
AI07731b
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M58WR064FT, M58WR064FB
Figure 21. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)
1 START POINT A 2 3 4 5 6 7 8
B
C
D
E
F
G
END POINT
AI07755
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M58WR064FT, M58WR064FB
PART NUMBERING
Table 26. Ordering Information Scheme
Example: Device Type M58 Architecture W = Multiple Bank, Burst Mode Operating Voltage R = VDD = 1.7V to 2V, VDDQ = 1.7V to 2.24V Device Function 064FT = 64 Mbit (x16), Top Boot 064FB = 64 Mbit (x16), Bottom Boot Speed 60 = 60ns 70 = 70ns 80 = 80ns Package ZB = VFBGA56: 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch Temperature Range 6 = -40 to 85C Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M58WR064FT 70 ZB 6 T
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M58WR064FT, M58WR064FB
Table 27. Daisy Chain Ordering Scheme
Example: Device Type M58WR064F Daisy Chain ZB = VFBGA56: 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M58WR064F -ZB T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M58WR064FT, M58WR064FB
APPENDIX A. BLOCK ADDRESS TABLES
Table 28. Top Boot Block Addresses, M58WR064FT
Bank # 0 1 2 3 4 Parameter Bank 5 6 7 8 9 10 11 12 13 14 15 16 17 Bank 1 18 19 20 21 22 23 24 25 Bank 2 26 27 28 29 30 31 32 33 Bank 3 34 35 36 37 38 Bank 4 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF Bank 5 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF Bank 6 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF Bank 7 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF Bank 8 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF
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M58WR064FT, M58WR064FB
79 80 81 Bank 9 82 83 84 85 86 87 88 89 Bank 10 90 91 92 93 94 95 96 97 Bank 11 98 99 100 101 102 103 104 105 Bank 12 106 107 108 109 110 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF Bank 15 Bank 14 Bank 13 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
Note: There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
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M58WR064FT, M58WR064FB
Table 29. Bottom Boot Block Addresses, M58WR064FB
Bank # 134 133 132 Bank 15 131 130 129 128 127 126 125 124 Bank 14 123 122 121 120 119 118 117 116 Bank 13 115 114 113 112 111 110 109 108 Bank 12 107 106 105 104 103 102 101 100 Bank 11 99 98 97 96 95 Bank 10 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF Bank 9 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF Bank 8 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF Bank 7 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF Bank 6 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF
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54 53 52 Bank 5 51 50 49 48 47 46 45 44 Bank 4 43 42 41 40 39 38 37 36 Bank 3 35 34 33 32 31 30 29 28 Bank 2 27 26 25 24 23 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF Parameter Bank Bank 1 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF 000000-000FFF
Note: There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
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APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 30, 31, 32, 33, 34, 35, 36, 37, 38 and 39 show the adTable 30. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
dresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 5., Protection Register Memory Map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to Read mode.
80h
Security Code Area
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 31, 32, 33 and 34. Query data is always presented on the lowest order data outputs.
Table 31. CFI Query Identification String
Offset 00h 01h 02h 03h 04h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Sub-section Name 0020h 8810h 8811h reserved reserved reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0039h 0000h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 34.) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 39h NA NA Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved Reserved Reserved "Q" "R" "Y" Description Value ST Top (M58WR064FT) Bottom (M58WR064FB)
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Table 32. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for multi-Byte programming = 2n s Typical time-out per individual block erase = 2n ms Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2n times typical Maximum time-out for multi-Byte programming = 2n times typical Maximum time-out per individual block erase = 2n times typical Maximum time-out for chip erase = 2n times typical Value 1.7V
1Ch
0020h
2V
1Dh
00B4h
11.4V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C6h 0004h 0000h 000Ah 0000h 0003h 0000h 0002h 0000h
12.6V 16s NA 1s NA 128s NA 4s NA
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Table 33. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh M58WR064FT 2Fh 30h 31h 32h 33h 34h 35h 38h 2Dh 2Eh M58WR064FB 2Fh 30h 31h 32h 33h 34h 35h 38h Data 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h reserved 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h reserved Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Region 1 Information Number of identical-size erase blocks = 007Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase blocks = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Reserved for future erase block region information Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 007Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Reserved for future erase block region information Value 8 MByte x16 Async. NA 2 127 64 KByte 8 8 KByte NA 8 8 KByte 127 64 KByte NA
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Table 34. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 39h Data 0050h 0052h 0049h (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0033h 00E6h 0003h (P+7)h = 40h (P+8)h = 41h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported(1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "3"
(P+9)h = 42h
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0'
(P+A)h = 43h (P+B)h = 44h
0003h 0000h
Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance)
Yes Yes
(P+C)h = 45h
0018h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage
1.8V
(P+D)h = 46h
00C0h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV
12V
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Table 35. Protection Register Information
Offset (P+E)h = 47h (P+F)h = 48h (P+10)h = 49h (P+11)h = 4Ah (P+12)h= 4Bh Data 0001h 0080h 0000h 0003h 0004h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region Value 1
0080h 8 Bytes 16 Bytes
Table 36. Burst Read Information
Offset (P+13)h = 4Ch Data 0003h Description Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Value 8 Bytes
(P+14)h = 4Dh (P+15)h = 4Eh
0004h 0001h
4 4
(P+16)h = 4Fh (P+17)h = 50h (P+18)h = 51h
0002h 0003h 0007h
8 16 Cont.
Table 37. Bank and Erase Block Region Information
M58WR064FT(top) Offset (P+19)h = 52h Data 02h M58WR064FB (bottom) Description Offset (P+19)h = 52h Data 02h Number of Bank Regions within the device
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.
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Table 38. Bank and Erase Block Region 1 Information
M58WR064FT (top) Offset (P+1A)h = 53h (P+1B)h = 54h (P+1C)h = 55h Data 0Fh 00h 11h M58WR064FB (bottom) Description Offset (P+1A)h = 53h (P+1B)h = 54h (P+1C)h = 55h Data 01h 00h 11h Number of program or erase operations allowed in region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) Number of identical banks within Bank Region 1
(P+1D)h = 56h
00h
(P+1D)h = 56h
00h
(P+1E)h = 57h
00h
(P+1E)h = 57h
00h
(P+1F)h = 58h
01h
(P+1F)h =58h
02h
(P+20)h = 59h (P+21)h = 5Ah (P+22)h = 5Bh (P+23)h = 5Ch (P+24)h = 5Dh (P+25)h = 5Eh
07h 00h 00h 01h 64h 00h
(P+20)h = 59h (P+21)h = 5Ah (P+22)h = 5Bh (P+23)h = 5Ch (P+24)h = 5Dh (P+25)h = 5Eh
07h 00h 20h 00h 64h 00h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved 5Eh 01 5Eh 01 Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+26)h = 5Fh
01h
(P+26)h = 5Fh
01h
(P+27)h = 60h
03h
(P+27)h = 60h
03h
(P+28)h = 61h (P+29)h = 62h (P+2A)h = 63h (P+2B)h = 64h (P+2C)h = 65h (P+2D)h = 66h
06h 00h 00h 01h 64h 00h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
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M58WR064FT (top) Offset Data M58WR064FB (bottom) Description Offset Data Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+2E)h = 67h
01h
(P+2F)h = 68h
03h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.
Table 39. Bank and Erase Block Region 2 Information
M58WR064FT (top) Offset (P+28)h = 61h (P+29)h = 62h Data 01h 00h M58WR064FB (bottom) Description Offset (P+30)h = 69h (P+31)h = 6Ah Data 0Fh Number of identical banks within bank region 2 00h Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2)
(P+2A)h = 63h
11h
(P+32)h = 6Bh
11h
(P+2B)h = 64h
00h
(P+33)h = 6Ch
00h
(P+2C)h = 65h
00h
(P+34)h = 6Dh
00h
(P+2D)h = 66h
02h
(P+35)h = 6Eh
01h
(P+2E)h = 67h (P+2F)h = 68h (P+30)h = 69h (P+31)h = 6Ah (P+32)h = 6Bh (P+33)h = 6Ch
06h 00h 00h 01h 64h 00h
(P+36)h = 6Fh (P+37)h = 70h (P+38)h = 71h (P+39)h = 72h (P+3A)h = 73h (P+3B)h = 74h
07h 00h 00h 01h 64h 00h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+34)h = 6Dh
01h
(P+3C)h = 75h
01h
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M58WR064FT (top) Offset Data M58WR064FB (bottom) Description Offset Data Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in Table 36.) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+35)h = 6Eh
03h
(P+3D)h = 76h
03h
(P+36)h = 6Fh (P+37)h = 70h (P+38)h = 71h (P+39)h = 72h (P+3A)h = 73h (P+3B)h = 74h
07h 00h 20h 00h 64h 00h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in Table 36.) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3E)h = 77h (P+3F)h = 78h Feature Space definitions Reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+3C)h = 75h
01h
(P+3D)h = 76h
03h
(P+3E)h = 77h (P+3F)h = 78h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.
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APPENDIX C. FLOWCHARTS AND PSEUDO CODES
Figure 22. Program Flowchart and Pseudo Code
Start program_command (addressToProgram, dataToProgram) {: " writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ " writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
Write 40h or 10h (3)
Write Address & Data
Read Status Register (3)
SR7 = 1
AI06170b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
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Figure 23. Double Word Program Flowchart and Pseudo code
Start
Write 35h
Write Address 1 & Data 1 (3, 4)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (addressToProgram1, 0x35); /*see note (4)*/ writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (addressToProgram) ; "see note (4)" /* E or G must be toggled*/
Read Status Register (4)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.SR7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06171b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. 4. Any address within the bank can equally be used.
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Figure 24. Quadruple Word Program Flowchart and Pseudo Code
Start
Write 56h
Write Address 1 & Data 1 (3, 4)
quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (addressToProgram1, 0x56); /*see note (4) */ writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (addressToProgram) ; /"see note (4) "/ /* E or G must be toggled*/
Write Address 2 & Data 2 (3)
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3)
Read Status Register (4)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.SR7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR==1) /*program to protect block error */ error_handler ( ) ;
}
AI06977b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1. 4. Any address within the bank can equally be used.
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Figure 25. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ;
Write FFh
YES Write FFh
Read Data
Read data from another address
read_data ( ); /*read data from another address*/
Write D0h
writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/
Write 70h(1) } Program Continues with Bank in Read Status Register Mode }
writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */
AI10117b
Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
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Figure 26. Block Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* only A12-A21 are significant */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/
Write 20h (2)
Write Block Address & D0h
Read Status Register (2)
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI10526
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can be used also.
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Figure 27. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
Write FFh
Read Data YES Write FFh Read data from another block or Program/Protection Register Program or Block Lock/Unlock/Lock-Down Write D0h else }
read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/
{ writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } }
Write 70h(1)
Erase Continues with Bank in Read Status Register Mode
Note: The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
AI10116b
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Figure 28. Locking Operations Flowchart and Pseudo Code
Start
Write 60h (1)
locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */
Write 01h, D0h or 2Fh
Write 90h (1)
Read Block Lock States
Locking change confirmed? YES Write FFh (1)
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ }
End
AI06176b
Note: 1. Any address within the bank can equally be used.
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Figure 29. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h (3)
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ;
Write Address & Data
Read Status Register (3)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
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Figure 30. Enhanced Factory Program Flowchart
SETUP PHASE Start Write 30h Address WA1 Write D0h Address WA1 Write PD1 Address WA1(1) VERIFY PHASE
Read Status Register
Read Status Register SR0 = 0? NO SR7 = 0? YES Write PD2 Address WA2(1) NO NO
Check SR4, SR3 and SR1 for program, VPP and Lock Errors Exit PROGRAM PHASE
YES SR0 = 0? YES Write PD1 Address WA1
Read Status Register
Read Status Register
SR0 = 0? YES NO Write PDn Address WAn(1)
NO
SR0 = 0? YES Write PD2 Address WA2(1)
Read Status Register
Read Status Register
NO SR0 = 0? YES
SR0 = 0? YES Write PDn Address WAn(1)
NO
Write FFFFh Address = Block WA1 / EXIT PHASE Read Status Register
Read Status Register
SR7 = 1? YES
NO
SR0 = 0? YES Write FFFFh Address = Block WA1 /
NO Check Status Register for Errors
End
AI06160
Note: 1. Address can remain Starting Address WA1 or be incremented.
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Enhanced Factory Program Pseudo Code
efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } }
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Figure 31. Quadruple Enhanced Factory Program Flowchart
SETUP PHASE Start Write PD1 Address WA1(1) LOAD PHASE
Write 75h Address WA1 FIRST LOAD PHASE
Write PD1 Address WA1
Write PD2 Address WA2(2)
Read Status Register
Write PD3 Address WA3(2)
NO SR7 = 0? YES Write PD4 Address WA4(2) EXIT PHASE Check SR4, SR3 and SR1 for program, VPP and Lock Errors PROGRAM AND VERIFY PHASE
Read Status Register
Write FFFFh Address = Block WA1 /
Exit Check SR4 for Programming Errors
NO SR0 = 0?
YES Last Page? YES NO
End
AI06178b
Note: 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block. 2. The address is only checked for the first Word of each Page as the order to program the Words is fixed, so subsequent Words in each Page can be written to any address.
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Quadruple Enhanced Factory Program Pseudo Code
quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } } /*2nd data*/ writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.SR0==1) } /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler(); } }
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APPENDIX D. COMMAND INTERFACE STATE TABLES
Table 40. Command Interface States - Modify Table, Next State
Command Input Erase Confirm Block P/E DWP, Erase, Clear Quad- Resume, Program/ Read QWP Bank status EFP Erase Status Block EFP Setup Erase Register Setup (3,4) Unlock Suspend Register Setup Setup (5) (30h) (35h, (3,4) (B0h) (70h) confirm, (75h) (50h) 56h) (20h, EFP 80h) Confirm (D0h) Program Quad-EFP Erase Setup EFP Setup Ready Setup Setup Ready (Lock Error) Ready Ready (Lock Error) OTP Busy Program Busy Program Busy Program Suspended Ready (error) Erase Busy Erase Suspended Erase Busy Program Busy Erase Busy Erase Suspended Program Suspended Program Busy Program Suspended Ready (error) Erase Busy Erase Suspended
Current CI State
WP Read setup Array(2) (3,4) (FFh) (10/40h)
Read Electronic signature, Read CFI Query (90h, 98h)
Ready Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Busy Erase
Ready
Program Setup
Program in Erase Erase Suspend Suspended Suspend Setup Busy
Program Busy in Erase Suspend Program Busy in Erase Suspend Program Busy in Erase Suspend Erase Suspend EFP Busy EFP Busy (6) EFP Verify (6) Quad EFP Busy (6) Quad EFP Busy(6) Program Suspend in Erase Suspend Program Busy in Erase Suspend
Program in Erase Suspend
Suspend Lock/CR Setup in Erase Suspend Setup EFP Busy Verify Quad EFP Setup Busy
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend
Erase Suspend (Lock Error) Ready (error)
Erase Suspend (Lock Error) Ready (error)
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to `0'.EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data.
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Table 41. Command Interface States - Modify Table, Next Output
Command Input (6) Erase Confirm P/E Resume, Program/ QuadErase Block EFP Suspend Unlock Setup (B0h) confirm, (75h) EFP Confirm (D0h)
Current CI State
Read Array(2) (FFh)
DWP, QWP Setup
(3,4)
Block Erase, Bank Erase Setup
(3,4)
EFP Setup (30h)
(35h, 56h)
Read Status Register (70h)
Clear status Register
(5)
(50h)
(20h, 80h) Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy Erase Busy Program/Erase Program Busy in Erase Suspend Program Suspend in Erase Suspend
Read Electronic signature, Read CFI Query (90h, 98h)
Status Register
Status Register
Array
Status Register
Output Unchanged
Status Register
Output Unchanged
Electronic Signature/ CFI
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode, depending on the command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the bank's output state.
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Table 42. Command Interface States - Lock Table, Next State
Command Input Current CI State Lock/CR Setup(4) (60h) Lock/CR Setup OTP Setup(4) (C0h) OTP Setup Ready OTP Busy Program Busy Program Busy Program Suspended Ready (error) Erase Busy Lock/CR Setup in Erase Suspend Block Block Lock Lock-Down Confirm Confirm (01h) (2Fh) Set CR Confirm (03h) Ready Ready (Lock error) EFP Exit, Quad EFP Exit (3) Illegal Command
(5)
P/E. C. Operation Completed N/A N/A N/A Ready N/A Ready N/A N/A Ready
Ready Lock/CR Setup OTP Setup Busy Setup Program Busy Suspend Setup Busy Erase Suspend
Ready (Lock error)
Erase Suspended
N/A
Setup Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Setup EFP Busy Verify Setup QuadEFP Busy Erase Suspend (Lock error)
Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend Erase Suspend Ready (error) EFP Busy (2) EFP Verify
(2)
N/A Erase Suspended N/A Erase Suspend (Lock error) EFP Busy(2) EFP Verify(2) N/A N/A EFP Verify Ready N/A Ready N/A Ready Quad EFP Busy(2) Ready
Quad EFP Busy (2) Quad EFP Busy (2)
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to `0'. EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data. 3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 4. If the P/E.C. is active, both cycles are ignored. 5. Illegal commands are those not defined in the command set.
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Table 43. Command Interface States - Lock Table, Next Output
Current CI State Lock/CR Setup(3) (60h) OTP Setup(3) (C0h) Block Lock Confirm (01h) Command Input Block Set CR Lock-Down Confirm Confirm (03h) (2Fh) EFP Exit, Quad EFP Exit (2) Illegal Command
(4)
P/E. C. Operation Completed
Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy EraseBusy Program/Erase Program Busy in Erase Suspend Program Suspend in Erase Suspend
Status Register
Status Register
Array
Status Register
Output Unchanged
Status Register
Output Unchanged
Array
Output Unchanged
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 3. If the P/E.C. is active, both cycles are ignored. 4. Illegal commands are those not defined in the command set.
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REVISION HISTORY
Table 44. Document Revision History
Date 18-Oct-2002 Version 1.0 First Issue Synchronous Burst Read Suspend and Figure 14., Synchronous Burst Read Suspend AC Waveforms, added. 16-Word burst and 16 Word boundary added. Security Block removed from the document. Automatic Standby mode explained under Asynchronous Read Mode. Minor text change in Clear Status Register Command. Bank Erase Command moved to Factory Program Commands section. Number of Bank Erase cycles limited to 100. Erase replaced by Block Erase in Tables 11 and 12, Dual Operations Allowed in Other Banks and the Same Bank, respectively. VPP = VPPH test condition for IPP2 removed from Table 18., DC Characteristics Currents. Overbar removed from WAIT signal in Read AC Waveforms (Figures 10, 11, 12 and 13). tEHEL parameter changed for 70 and 80 class speeds in Table 21., Synchronous Read AC Characteristics. Package mechanical data corrected (Table 25.). Data reserved at addresses 35h and 38h (Table 33). Data and Value modified at address offset (P+14)h = 4Dh. 16 Word burst added to Table 36., Burst Read Information, and subsequent address offsets shifted by one (Tables 37, 38 and 39). Note to Table 30., Query Structure Overview, modified. VDD and VDDQ voltage ranges limited to 1.7V to 2V and 1.7V to 2.24V, respectively; VDDQmax modified accordingly in Table 15., Absolute Maximum Ratings. VPP1 parameter modified in Table 19., DC Characteristics - Voltages. Alt symbols for tEHEL and tELEH corrected in Table 23., Write AC Characteristics, Chip Enable Controlled. Cross-references corrected. Address lines corrected in Figure 14., Synchronous Burst Read Suspend AC Waveforms. Connection added to Figure 20., VFBGA56 Daisy Chain - Package Connections (Top view through package). Lead-free package options added to Table 26., Ordering Information Scheme, and Table 27., Daisy Chain Ordering Scheme. CFI information modified: at addresses 1Ch, 1Dh, 1Eh, 20h and 24h in Table Table 32.; at address 2Ah in Table 33.; at address (P+4)h = 3Dh in Table 34.; at address (P+18)h = 51h in Table 36. and at address (P+38)h = 71h in Table 39. M58WR064FP and M58WR064FQ Part Numbers added. VPP protection feature disabled in the M58WR064FP and M58WR064FQ. Set Configuration Register Command clarified. PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES section modified. 16 Word burst test condition added for f=40MHz and f=54MHz, and 66MHz burst frequency added in Table 18., DC Characteristics - Currents. VPP1 Min and VPPLK Max corrected in Table 19., DC Characteristics - Voltages. tGHQZ parameter corrected for speed classes 70ns and 80ns in Table 20., Asynchronous Read AC Characteristics. M58WR064FP and M58WR064FQ Part Numbers removed. Typical values for Bank Erase and Main Block Erase (not preprogrammed), and for Parameter and Main Block Program when VPP = VDD modified in Table 14., Program/ Erase Times and Endurance Cycles. Typical values for Erase and Bank Program when VPP = VPPH modified in Table 14., Program/Erase Times and Endurance Cycles. IDD1 parameters for Synchronous Read at f = 40MHz removed from Table 18., DC Characteristics - Currents. Small text changes. Document status promoted from Product Preview to Preliminary Data. IDD6 values for Program/Erase in one Bank, Synchronous Read in another Bank modified in Table 18., DC Characteristics - Currents. AC Waveforms simplified. APPENDIX C. and APPENDIX D. revised. Small text changes. Product fully Compliant with the ST ECOPACK specification. Document Status promoted from Preliminary Data to Full Datasheet. Revision Details
12-Mar-2003
2.0
12-May-2003
2.1
11-Dec-2003
3.0
15-Apr-2004
4.0
08-Oct-2004
5.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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